Features on semiconductor wafers and dies are three-dimensional structures and a complete characterization must describe not just a surface dimension, such as the top width of a line or trench, but a complete three-dimensional profile of the feature. Process engineers must be able to accurately measure the critical dimensions (CD) of such surface features to fine tune the fabrication process and assure a desired device geometry is obtained.
Typically, such CD measurements are made using instruments such as a scanning electron microscope (SEM). In a scanning electron microscope (SEM), a primary electron beam is focused to a fine spot that scans the surface to be observed. Secondary electrons are emitted from the surface as it is impacted by the primary beam. The secondary electrons are detected, and an image is formed, with the brightness at each point of the image being determined by the number of secondary electrons detected when the beam impacts a corresponding spot on the surface. As features continue to get smaller and smaller, however, there comes a point where the features to be measured are too small for the resolution provided by an ordinary SEM.
As semiconductor geometries continue to shrink, manufacturers increasingly rely on transmission electron microscopes (TEMs) for monitoring the process, analyzing defects, and investigating interface layer morphology. TEMs allow observers to see features having sizes on the order of nanometers, and to see the internal structure of a sample. The sample must be sufficiently thin to allow many of the electrons in the primary beam to travel though the sample and exit on the opposite site.
Because a sample must be very thin for viewing with transmission electron microscopy (whether TEM or STEM), preparation of the sample can be delicate, time-consuming work. The term “TEM” as used herein refers to a TEM or a STEM and references to preparing a sample for a TEM are to be understood to also include preparing a sample for viewing on an STEM. TEM samples are typically less than 100 nm thick, but for some applications samples must be considerably thinner. With advanced processes at 30 nm, 22 nm, and below, the sample needs to be less than 20 nm in thickness in order to avoid overlap among small scale structures. The precision and accuracy involved in producing such samples is typically very time consuming. In fact, even though the information that can be discovered by TEM analysis can be very valuable, the entire process of creating and measuring TEM samples has historically been so labor intensive and time consuming that it has not been practical to use this type of analysis for manufacturing process control. While the use of focused ion beam (FIB) methods in sample preparation has reduced the time required to prepare samples for TEM analysis down to only a few hours, it is not unusual to analyze 15 to 50 TEM samples from a given wafer. As a result, speed of sample preparation is a very important factor in the use of TEM analysis, especially for semiconductor process control.
FIG. 4 illustrates a prior art automated S/TEM sample management (available commercially as the ExSolve™ system) according to described in U.S. Pat. No. 8,890,064 to Arjavac et al. The ExSolve wafer TEM prep (WTP) workflow addresses the needs of facilities that require automated, high-throughput sampling at advanced technology nodes. It complements the capabilities of dual beam systems such as the FEI company's Helios NanoLab™ DualBeam™ 1200AT, which provides more flexible, operator-directed, sample preparation methods, along with additional capabilities such as high-resolution scanning electron microscopy (SEM) imaging and analysis.
In the depicted system of FIG. 4, TEM samples are processed by a cluster of different processing tools having the capability of sequentially processing samples (e.g., lamellae extracted from semiconductor wafers). The S/TEM sample management tool suite 100 generally includes a Process Controller 110 and a Fab Host computer 112 operably connected to (or integrated with) a FIB system 114, a lamella extraction tool 116 such as an Ex-Situ Plucker (“ESP”), and a S/TEM system 118. FIB system 114 may comprise a dual beam FIB/SEM system such as the Certus™/CLM available from FEI Company of Hillsboro, Oreg., the assignee of the present invention; and S/TEM system 118 may comprise a system such as a Tecnai™ G2 S/TEM also available from FEI Company. In the system of FIG. 4, each processing tool is operably connected to (or integrated with) a computer station 120, which uses software 122 for implementing TEM sample creation and processing. Any suitable software (conventional and/or self-generated) applications, modules, and components may be used for implementing software. For example, in the system of FIG. 4, the automated S/TEM sample management is implemented using IC3D™ software for automated machine control and metrology, which is also available from FEI Company.
However, even in such automated systems, the requirement for manual intervention at various recipe creation steps such as specifying and verifying fiducial locations slows down the process. The time and number of representative samples required to develop/create a fully automated TEM sample preparation recipe (or “TEM prep recipe”) is too long to enable leading semiconductor manufacturers to realize “time to data” in an automated workflow for both process monitoring and defect root cause analysis. Foundry-type manufactures are specifically challenged due to the large number of different wafers for different fabless customers. By the time they develop a robust recipe, the pattern may have changed so a new recipe would have to be developed. Recipe development time must be reduced and optimally automated to enable foundry customers to realize the benefits of fully automated TEM Prep.
For TEM prep, the problem is presently solved by skilled engineers creating the recipe in an advanced visual scripting authoring software framework that enables automation of a wide range of instrument control commands and imaging tasks (the iFAST™ software by FEI) software on an automated, high-throughput sample preparation system that can prepare site-specific lamellae (the ExSolve™ system described briefly above), creating test samples, and manually analyzing samples in offline TEM. The learning is then applied to the recipe parameters and the process is iterated. However, such a process is relatively slow and resource intensive, and not readily scalable. Recipe creation/development for a fully automated TEM prep processing can be a time consuming and applications engineering intensive activity due to lack of pre-determined knowledge of pattern information available on wafer/sample.